The present invention relates to a data processing device with a memory coupling unit. Data processing devices, such as microprocessors or microcontrollers comprise one or more register files for intermediate storage of data and addresses. For processing of data and/or addresses, the content of these registers has to be loaded and stored into a memory subsystem which can consist of standard memory and/or a cache memory. Usually, an interface between the register file and the memory subsystem is provided which is controlled by respective control units of the microprocessor during load and store cycles.
Modern microprocessors provide superscalar design with the ability of processing multiple instructions in parallel. Furthermore, in digital signal processing some instructions require multiple data which is processed during execution of the respective instruction. The interface between the register file and the memory can be a bottleneck within the processing path and slow down the over all speed of the respective microprocessor.
It is therefore an object of the invention to provide an interface between a register file and a memory system with high speed access to data stored in the memory system.
This object is achieved by a data processing unit with a register file having a plurality of registers, a memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks. The coupling unit comprises a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank or the register file selectively with one of the sub-busses, and second couplers for coupling the register file or the memory banks with the bus.
In another embodiment of the present invention, the data processing unit comprises a first and a second register file having a plurality of registers, a memory having a plurality of n-bit input/output ports, a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank selectively with one of the sub-busses, second couplers for coupling the first register file with the bus, and third couplers for coupling the second register file with the bus.
In yet another embodiment a data processing unit comprises a first and a second register file having a plurality of registers, a first and second memory each having a plurality of n-bit input/output ports, a first bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank of said first memory selectively with one of the sub-busses, second couplers for coupling said first register file with said first bus, a second bus having a bus width of at least 2n-bits forming at least a third and fourth sub-bus, third couplers for coupling each memory bank of said second memory selectively with one of the sub-busses, fourth couplers for coupling the second register file with the second bus, and a bus-coupler for coupling the first and second bus.